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copyright ? 201 3 future technology devices international limited 1 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 future technology devices international ltd . ft313h ( usb 2.0 hs embedded host controller ) the ft313h is a hi - speed universal serial bus ( usb ) host controller compatible with universal serial bus specification rev 2.0 and support s data transfer speeds of up to 480m bit/s. the ft313h has the following advanced features: ? single chip usb 2.0 hi - speed compatible . ? compatible to e nhance d host controller interface specification rev 1.0 . ? the usb1.1 host is integrated into the usb2.0 ehci compatible host controller. ? single usb host port . ? supports data transfer at high - speed (480m bit/s), full - speed (12m bit/s), and low - speed (1.5m bit/s) . ? supports the isochronous, interrupt, control, and bulk transfers. ? supports the split transact ion for high - speed hub and the preamble transaction for full - speed hub. ? supports multiple processor interface s with 8 - bit or 16 - bit bus : sram, no r flash, and general multiplex . ? single configurable interrupt (int) line for host controller . ? integrated 24 k b high speed ram memory . ? supports dma operation. ? integrated phase - locked loop (pll) supports external 12mhz, 19.2mhz, and 24mhz crystal, and direct external clock source input. ? low power consumption for portable application . ? s upports bus interface i/o voltage from 1.6 2 v to 3.6 3 v . ? supports hybrid power mode; vcc ( 3v3 ) is not present, vcc ( i / o ) is powered . ? internal voltage regulator supplies 1.2v to the digital core. ? supports battery charg ing specification rev 1.2. ? the downstream port can be configured as sdp, cdp or dcp. ? supports vbus power switching and over current control . ? - 40c to 85c extended operating temperature range. ? available in compact pb - free 64 pin qfn , l qfp and t qfp packages ( all rohs compliant) . neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or re produced in any material or electronic form without the prior written consent of the copyright holder. this product and its documen tation are supplied on an as - is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd will not accept any claim for damages howsoever arising as a result of use or fa ilure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injur y. this document provides preliminary information that may be subject to change without notice. no freedom to use patents or other intellectual property rights is implied by the publication of this document. future technology devices international ltd, uni t 1, 2 seaward place, centurion business park , glasgow g41 1hh united kingdom. scotland registered company number: sc136640
copyright ? 201 3 future technology devices international limited 2 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 1 typical applications ? tv/tv box ? printer ? i nstrumentation ? media player ? tablet ? set - top box 1.1 part numbers part number package ft313h q - x 64 pin qfn ft313h l - x 64 pin l qfp ft313h p - x 64 pin tqfp table 1 - 1 ft313h numbers note: packaging codes for x is: - r: taped and reel, (qfn is 3000pcs, lqfp is 1000 pcs, tqfp is 2500pcs per reel) - t: tray packing, ( qfn is 2600pcs, lqfp is 16 00 pcs, tqfp is 2500pcs per tray ) for example: ft313hq - r is 3000 qfn pcs in taped and reel packaging 1.2 usb compliant at the time of writing this datasheet, the ft313h was still to complete usb complianc e testing.
copyright ? 201 3 future technology devices international limited 3 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 2 ft313h block diagram figure 2 - 1 ft313h block diagram for a description of each function please refer to section 4. f t 3 1 3 h i n t e r f a c e c o n t r o l l o g i c d m a c o n t r o l l e r r a m 2 4 k b m e m o r y a r b i t e r e h c i c o m p a t i b l e h o s t c o n t r o l l e r a t x b c d r e g u l a t o r p o r p l l a d [ 1 5 : 0 ] a [ 7 : 0 ] a l e / a d v _ n c l e r d _ n / r e _ n / o e _ n c s _ n / c e _ n w r _ n / w e _ n i n t d r e q o c _ n r r e f d p d m p s w _ n c p e 0 v c c ( 3 v 3 ) v c c ( 1 v 2 ) g n d r e s e t _ n a g n d f r e q s e l 2 f r e q s e l 1 x 2 x 1 / c l k i n v c c ( i / o ) d a c k t e s t e n a g n d v b u s c p e 1 v o u t ( 1 v 2 )
copyright ? 201 3 future technology devices international limited 4 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 table of contents 1 typical applications ................................ ................................ ...... 2 1.1 part numbers ................................ ................................ ...................... 2 1.2 usb comp liant ................................ ................................ .................... 2 2 ft313h block diagram ................................ ................................ . 3 3 device pin out and signal description ................................ .......... 7 3.1 pin out C 64pin qfn ................................ ................................ ........... 7 3.2 pin out C 64pin lqfp ................................ ................................ .......... 8 3.3 pin out C 64pin tqfp ................................ ................................ .......... 9 3.4 pin description ................................ ................................ ................. 10 4 function description ................................ ................................ ... 14 4.1 microcontroller bus interface ................................ ........................... 14 4.2 sram bus interface mode ................................ ................................ . 15 4.3 nor bus interface mode ................................ ................................ ... 16 4.4 general multiplex bus interface mo de ................................ .............. 16 4.5 interface mode lock ................................ ................................ .......... 16 4.6 dma controller ................................ ................................ .................. 16 4.7 ehci h ost controller ................................ ................................ ......... 17 4.8 system clock ................................ ................................ ..................... 17 4.8.1 phase locked loop (pll) clock multiplier ................................ ................................ ...... 17 4.9 power management ................................ ................................ .......... 18 4.9.1 power up and reset sequence ................................ ................................ ...................... 18 4.9.2 power supply ................................ ................................ ................................ ............. 18 4.9.3 atx reference voltage ................................ ................................ ................................ 18 4.9.4 power modes ................................ ................................ ................................ ............ 18 4.10 bcd mode ................................ ................................ ...................... 19 5 host controller specific registers ................................ ................ 20 5.1 overview of registers ................................ ................................ ....... 20 5.2 ehci operational registers ................................ ................................ 21 5.2.1 hccaplength register (address = 00h) ................................ ................................ ....... 21 5.2.2 hcsparams register (address = 04h) ................................ ................................ .......... 21 5.2.3 hccparams register (address = 08h) ................................ ................................ .......... 22 5.2.4 usbcmd register (address = 10h) ................................ ................................ ............... 22 5.2.5 usbsts register (address = 14h) ................................ ................................ ................ 24 5.2.6 usbintr register (address = 18h) ................................ ................................ ............... 25 5.2.7 frindex register (address = 1ch) ................................ ................................ ............... 26 5.2.8 periodiclistaddr register (address = 24h) ................................ ............................... 26 5.2.9 asynclistaddr register (address = 28h) ................................ ................................ .... 26
copyright ? 201 3 future technology devices international limited 5 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 5.2.10 postsc register (address = 30h) ................................ ................................ ............. 27 5.3 configuration registers ................................ ................................ ..... 29 5.3.1 eottime register (address = 34h) ................................ ................................ ............... 29 5.3.2 chipid register (address = 80h) ................................ ................................ ................. 30 5.3.3 hwmode register (address = 84h) ................................ ................................ .............. 30 5.3.4 edgeintc register (address = 88h) ................................ ................................ ............. 31 5.3.5 swreset register (address = 8ch) ................................ ................................ .............. 31 5.3.6 memaddr register (address = 90h) ................................ ................................ ............. 33 5.3.7 dataport register (address = 92h) ................................ ................................ ............ 33 5.3.8 datasession register (address = 94h) ................................ ................................ ....... 33 5.3.9 config register (address = 96h) ................................ ................................ ................ 33 5.3.10 aux_memaddr register (address = 98h) ................................ ................................ .. 35 5.3.11 aux_dataport register (address = 9ah) ................................ ................................ . 35 5.3.12 sleeptimer register (address = 9ch) ................................ ................................ ...... 35 5.4 interrupt registers ................................ ................................ ............ 35 5.4.1 hcintsts register (address = a0h) ................................ ................................ ............. 35 5.4.2 hcinten register (address = a4h) ................................ ................................ ............... 37 5.5 usb testing registers ................................ ................................ ........ 38 5.5.1 testmode register (address = 50h) ................................ ................................ ............ 38 5.5.2 testpmset1 register (address = 70h) ................................ ................................ ......... 39 5.5.3 testpmset2 register (address = 74h) ................................ ................................ ......... 39 6 devices characteristics and ratings ................................ ........... 40 6.1 absolute maximum ratings ................................ ............................... 40 6.2 dc characteristics ................................ ................................ ............. 41 6.3 ac characteristics ................................ ................................ ............. 44 6.4 ti ming ................................ ................................ .............................. 46 6.4.1 pio timing ................................ ................................ ................................ ................ 46 6.4.2 dma timing ................................ ................................ ................................ ............... 52 7 applicatio n examples ................................ ................................ . 53 7.1 examples of bus interface connection ................................ .............. 54 7.1.1 16 - bit sram asynchronous bus interface ................................ ................................ ...... 54 7.1.2 8 - bit sram asynchronous bus interface ................................ ................................ ........ 54 7.1.3 16 - bit nor asynchronous bus interface ................................ ................................ ........ 55 7.1.4 8 - bit nor asynchronous bus interface ................................ ................................ .......... 55 7.1.5 16 - bit general multiplex asynchronous bus interface ................................ ...................... 55 7.1.6 8 - bit general multiplex asynchronous bus interface ................................ ........................ 56 8 package parameters ................................ ................................ ... 57 8.1 ft31 3h package markings ................................ ................................ 57 8.1.1 qfn - 64 ................................ ................................ ................................ .................... 57 8.1.2 lqfp - 64 ................................ ................................ ................................ ................... 58
copyright ? 201 3 future technology devices international limited 6 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8.1.3 t qfp - 64 ................................ ................................ ................................ ................... 59 8.2 qfn - 64 package dimensions ................................ ............................ 60 8.3 lqfp - 64 package dimensions ................................ ........................... 61 8.4 tqfp - 64 package dimensions ................................ ........................... 62 8.5 solder reflow profile ................................ ................................ ........ 63 9 ftdi chip contact information ................................ ................... 64 appendix a C references ................................ ................................ ........... 65 appe ndix b - list of figures and tables ................................ ..................... 65 appendix c - revision history ................................ ................................ .... 67
copyright ? 201 3 future technology devices international limited 7 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 3 device pin out and signal description 3.1 pin out C 64pin qfn figure 3 - 1 pin configuration qfn 64 (top - down view) 2 1 4 3 5 7 6 8 9 1 1 1 0 1 2 a d 3 v c c ( i / o ) a d 4 a d 5 a d 6 a d 7 a d 8 a d 9 1 3 1 5 1 4 1 6 a g n d a d 0 a d 1 a d 2 a d 1 0 a d 1 1 v c c ( i / o ) a d 1 2 a d 1 5 v c c ( 1 v 2 ) c s _ n / c e _ n r d _ n / r e _ n / o e _ n a 4 1 7 1 8 a d 1 3 a d 1 4 w r _ n / w e _ n i n t v c c ( i / o ) a 0 a 1 a 2 a 3 a 5 v c c ( 1 v 2 ) 4 3 4 4 4 1 4 2 4 0 3 8 3 9 3 7 3 6 3 4 3 5 3 3 4 7 4 8 4 5 4 6 a 6 a 7 d r e q a l e / a d v _ n c l e r e s e t _ n f r e q s e l 1 f r e q s e l 2 a g n d x 1 / c l k i n x 2 v o u t ( 1 v 2 ) a g n d p s w _ n r r e f o c _ n v b u s d m a g n d v c c ( 3 v 3 ) c p e 0 t e s t e n 5 0 4 9 f t d i x x x x x x x x x x f t 3 1 3 h q y y w w - b v c c ( i / o ) d a c k a g n d d p c p e 1 n c n c n c n c n c 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4
copyright ? 201 3 future technology devices international limited 8 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 3.2 pin out C 64pin l qf p figure 3 - 2 pin configuration l qfp64 (top - down view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 a g n d v b u s d m a g n d c p e 0 v c c ( 3 v 3 ) d p a g n d a d 0 a d 1 a d 2 a d 3 v c c ( i / o ) a d 4 a d 5 a d 6 a d 7 a d 8 a d 9 a 5 a d 1 2 a d 1 0 a d 1 1 v c c ( i / o ) i n t v c c ( i / o ) a 0 a 1 a 2 a 3 a 4 v c c ( i / o ) a 6 a 7 d r e q d a c k a l e / a d v _ n c l e r e s e t _ n f r e q s e l 1 f r e q s e l 2 a g n d x 1 / c l k i n 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 6 3 a d 1 3 a d 1 4 a d 1 5 c s _ n / c e _ n r d _ n / r e _ n / o e _ n w r _ n / w e _ n v c c ( 1 v 2 ) a g n d v o u t ( 1 v 2 ) x 2 p s w _ n o c _ n r r e f t e s t e n f t d i x x x x x x x x x x y y w w - b 6 4 v c c ( 1 v 2 ) c p e 1 n c n c n c n c n c f t 3 1 3 h l
copyright ? 201 3 future technology devices international limited 9 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 3.3 pin out C 64pin tqfp figure 3 - 3 pin configuration tqfp 64 (top - down view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 a g n d v b u s d m a g n d c p e 0 v c c ( 3 v 3 ) d p a g n d a d 0 a d 1 a d 2 a d 3 v c c ( i / o ) a d 4 a d 5 a d 6 a d 7 a d 8 a d 9 a 5 a d 1 2 a d 1 0 a d 1 1 v c c ( i / o ) i n t v c c ( i / o ) a 0 a 1 a 2 a 3 a 4 v c c ( i / o ) a 6 a 7 d r e q d a c k a l e / a d v _ n c l e r e s e t _ n f r e q s e l 1 f r e q s e l 2 a g n d x 1 / c l k i n 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 6 3 a d 1 3 a d 1 4 a d 1 5 c s _ n / c e _ n r d _ n / r e _ n / o e _ n w r _ n / w e _ n v c c ( 1 v 2 ) a g n d v o u t ( 1 v 2 ) x 2 p s w _ n o c _ n r r e f t e s t e n f t d i x x x x x x x x x x y y w w - b 6 4 v c c ( 1 v 2 ) c p e 1 n c n c n c n c n c f t 3 1 3 h p
copyright ? 201 3 future technology devices international limited 10 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 3.4 pin description pin no. name type description 1 agnd p a nalog g round 2 ad0 i/o bit 0 of the address and data bu s bidirectional pad; push - pull , three - state output. 3.3v tolerant 3 ad1 i/o bit 1 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 4 ad2 i/o bit 2 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 5 ad3 i/o bit 3 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 6 vcc ( i / o ) p i/o supply voltage; connect a 0.1uf decoupling capacitor 1.8v, 2.5v or 3.3v 7 ad4 i/o bit 4 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 8 ad5 i/o bit 5 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 9 ad6 i/o bit 6 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 10 ad7 i/o bit 7 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 11 ad8 i/o bit 8 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 12 ad9 i/o bit 9 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 13 ad10 i/o bit 10 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 14 ad11 i/o bit 11 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 15 vcc ( i / o ) p i/o supply voltage; connect a 0.1uf decoupling capacitor
copyright ? 201 3 future technology devices international limited 11 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 pin no. name type description 1.8v, 2.5v or 3.3v 16 ad12 i/o bit 12 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 17 ad13 i/o bit 13 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 18 ad14 i/o bit 14 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 19 ad15 i/o bit 15 of the address and data bus bidirectional pad; push - pull , three - state output. 3.3v tolerant 20 v cc (1v2) p core power 1.2 v input ; for normal opera tion, this pin must be con nected to pin 46. c onnect a 0.1uf decoupling capacitor 21 cs_n/ce_n i chip select; input ; 3.3 v tolerant 22 rd_n /re_n/oe_n i read enable, or read latch; when not in use, connect to vcc ( i / o ) input; 3.3 v tolerant 23 wr_n /we_n i write enable; when not in use, connect to vcc ( i / o ) input; 3.3 v tolerant 24 int o interrupt output push - pull output; 3.3 v tolerant 25 vcc ( i / o ) p i/o supply voltage; connect a 0.1uf decoupling capacitor 1.8v, 2.5v or 3.3v 26 a0 i bit 0 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant 27 a1 i bit 1 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant 28 a2 i bit 2 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant 29 a3 i bit 3 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant
copyright ? 201 3 future technology devices international limited 12 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 pin no. name type description 30 a4 i bit 4 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant 31 a5 i bit 5 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant 32 v cc (1v2) p core power 1.2 v input; for normal operation, this pin must be con nected to pin 46 . connect a 0.1uf decoupling capacitor. 33 a6 i bit 6 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant 34 a7 i bit 7 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant 35 vcc ( i / o ) p i/o supply voltage; connect a 0.1uf decoupling capacitor 1.8v, 2.5v or 3.3v 36 dreq o dma request; push - pull output; 3.3 v tolerant 37 dack i dma acknowledge; i nternal pull - down. input; 3.3 v tolerant 38 ale/adv_n i address latch enable input; 3.3 v tolerant 39 cle i command latch enable input; 3.3 v tolerant 40 reset_n i chip reset ; internal pull - up. input; 3.3 v tolerant 41 freqsel1 i input clock frequency selection pin1 input; 3.3 v tolerant 42 freqsel2 i input clock frequency selection pin2 input; 3.3 v tolerant 43 agnd p analog ground 44 x1/clkin ai crystal oscillator or clock input; 3.3 v peak input allowed 45 x2 ao crystal oscillator output; leave open if an external clock is applied on pin x1/clkin 46 v out (1v2) ao internal 1.2 v regulator output ; connect 4.7uf and
copyright ? 201 3 future technology devices international limited 13 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 pin no. name type description 0.1uf decoupling capacitor s to this pin . 47 agnd p analog ground 48 psw_n od port power switch; when not in use, connect to vcc(3v3) through a 10 k resistor vcc(3v3) through a 10k resistor ?1% resistor table 3 - 1 ft313h pin description notes: p : power or ground i : i nput o : output od : open drain output i/o : bi - direction input and output ai : analog input ao : analog output ai/o : analog input / output
copyright ? 201 3 future technology devices international limited 14 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 4 function description the ft313h is a usb2.0 compatible ehci single port host controller which is mainly composed of the following: ? microcontroller bus interface ? sram bus interface mode ? nor bus interface mode ? general multiplex bus interface mode ? interface mode lock ? dma controller ? ehci host controller ? system clock ? power management ? bcd mode the functions for each block are briefly described in the following subsections. 4.1 microcontroller bus interface the ft313h has a fast advance general purpose interface to communicate with most types of microcontrollers and microprocessors . this microcontroller interface is configured using pins ale/adv_n and cle to accommodate most types of interfaces. the bus interface supports 8 - bit and 16 - bit, which can be configured using bit data_bus_width. three bus interface types are selected using inputs ale/adv_n and cle during power up, the rd_n /re_n/oe_n and cs_n/ce_n pins, or the reset_n pin. table 4.1 provides detail of bus configuration for each mode. table 4.2 shows pinout information of each bus interface. bus mode ale/adv_n cle data_bus _width signal description sram 8 - bit high high 1 ? a[7:0]: 8 - bit address bus ? ad[7:0]: 8 - bit data bus ? write (wr_n), read (rd_n), chip select (cs_n): control signals for normal sram mode ? dack: dma acknowledge input ? dreq: dma request output sram 16 - bit high high 0 ? a[7:0]: 8 - bit address bus ? ad[15:0]: 16 - bit data bus ? write (wr_n), read (rd_n), chip select (cs_n): control signals for normal sram mode ? dack: dma acknowledge input ? dreq: dma request output nor 8 - bit high low 1 ? ad[7:0]: 8 - bit data bus ? adv_n, write enable, output enable, chip select: control signals nor 16 - bit high low 0 ? ad[15:0]: 16 - bit data bus ? adv_n, write enable, output enable, chip select: control signals general multiple x 8 - bit low high 1 ? ad[7:0]: 8 - bit data bus ? ale, write(wr_n), read(rd_n), chip
copyright ? 201 3 future technology devices international limited 15 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bus mode ale/adv_n cle data_bus _width signal description select: control signals ? dack: dma acknowledge input ? dreq: dma request output general multiple x 16 - bit low high 0 ? ad[15:0]: 16 - bit data bus ? ale, write(wr_n), read(rd_n), chip select: control signals ? dack: dma acknowledge input ? dreq: dma request output table 4 - 1 bus configuration modes sram mode nor mode general multiple x mode type description ad[15:0] ad[15:0] ad[15:0] i/o data or address bus a[7:0] - - i address bus - adv_n ale i address or command valid cs_n cs_ n cs_ n i chip select rd_n /re_ n oe_n rd_n/re_n i read control wr_n/we_n we_n wr_n/we_n i write control int int int o interrupt request dreq - dreq o dma request dack - dack i dma acknowledge table 4 - 2 pin information of the bus interface 4.2 sram bus interface mode the bus interface will be in sram 16 - bit mode if pins ale/adv_n and cle are high, when: ? the cs_n/ce_n pin goes low, and the rd_n /re_n/oe_n pin goes low . then, i f the data_bus_width bit is set, the bus interface will be in sram 8 - bit mode. in sram mode, a[7:0] is the 8 - bit address bus and ad[15:0] is the separate 16 - bit data bus. the ft313h pins rd_n /re_n/oe_n and wr_n /we_n are the read and write strobes. the sram bus interface supports both 8 - bit and 16 - bit bus width that can be configured by setting or clearing bit data_bus_width. the dma transfer is also applicable to this interface.
copyright ? 201 3 future technology devices international limited 16 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 4.3 nor bus interface mode the bus interface will be in nor 16 - bit mode, if pin ale/adv_n is high and pin cle is low, when: ? the cs_n/ce_n pin goes low, and the rd_n /re_n/oe_n pin goes low . then, i f the data_bus_width bit is set, the bus interface will be in nor 8 - bit mode. the nor flash interface access consists of two phases: address and data. the address is valid when cs_n/ce_n and adv_n are low, and the address is latched at the rising edge of adv_n. for a read operation, we_n must be high. oe_n is the data output control. when active, the addressed register or the buffer data is driven to the i/o bus. the read operation is completed when cs_n/ce_n is de - asserted. for a write operation, oe_n mu st be high. the we_n assertion can start when adv_n is de - asserted. we_n is the data input strobe signal. when de - asserted, data will be written to the addressed register or the buffer. the write operation is completed when cs_n/ce_n is de - asserted. 4.4 gener al multiplex bus interface mode the bus interface will be in general multiplex 16 - bit mode, if pin ale/adv_n is low and pin cle is high, when: ? the cs_n/ce_n pin goes low, and the rd_n /re_n/oe_n pin goes low . then, if the data_bus_width bit is set, the bus interface will be in general multiplex 8 - bit mode. the general multiplex bus interface supports most advance application processors. the general multiplex interface access consists of two phases: address and data. the address is valid when ale/adv_n goes high, and the address is latched at the falling edge of ale/adv_n. for a read operation, wr_n /we_n must be high. rd_n /re_n/oe_n is the data output control. when active, the addressed register or the buffer data is driven to the i/o bus. the read operation is completed when cs_n/ce_n is de - asserted. for a write operation, rd_n /re_n/oe_n must be high. the wr_n /we_n assertion can start when ale/adv_n is de - asserted. wr_n /we_n is the data input strobe signal. when de - asserted, data will be written to the addressed register or the buffer. the write operation is completed when cs_n/ce_n is de - asserted. the dma transfer is also applicable to this interface. 4.5 interface mode lock the bus in terface can be locked in any of the modes, sram, nor, or general multiplex, using bit 3 of the hw mode control register. to lock the interface in a particular mode: 1. read bits 7 and 6 of the sw reset register. 2. set bit 3 of the hw mode control register to lo gic 1. 3. read bits 7 and 6 of the sw reset register to ensure that the interface is locked in the desired mode. note: the default is 16 - bit sram mode. 4.6 dma controller the dma controller of the ft313h is used to transfer data between the system memory and local buffers. it shares data bus ad[15:0] and control signals wr_n /we_n, rd_n /re_n/oe_n, and cs_n/ce_n. the logic is dependent on the bus interface mode setting. dreq signal is from the ft313h to indicate the start of dma transfer. dack signal is used to differentiate if data transferred is for the dma or pio access. when dack is asserted, it indicates that it is still in dma mode. when dack is de - asserted, it indicates that pio is to be accessed. ale/adv_n and cle are ignored in a dma access cycle. correct data will be captured only on the rising edge of wr_n /we_n and rd_n /re_n/oe_n.
copyright ? 201 3 future technology devices international limited 17 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 the dma controller of the ft313h has only one dma channel. therefore, only one dma read or dma write may take place at a time. assign the dma transfer length in the data session length register for each dma transfer. if the transfer length is larger than the burst counter, the dreq signa l will de - assert at the end of each burst transfer. dreq will re - assert at the beginning of the each burst. when dma is transferring data from / to local buffer , if it want s to access local buffer content by pio mode, can use auxiliary memory access registers aux_memaddr and aux_dataport to read / write data from / to local buffer with single cycle. for a 16 - bit dma transfer, the minimum burst length is 2 bytes. this means that the burst length is only one dma cycle. therefore, dreq and dack will assert and de - assert at each dma cycle. the ft313h will be asserted dma eot interrupt to indicate that the dma transfer has either successfully completed or terminated. 4.7 ehci host controller the ft313h is a one - port ehci - compatible host controller which supports all the usb 2.0 compliant l ow - speed, f ull - speed, and h igh - speed devices and split/preamble transactions for the hs/fs hub. the ehci host controller supports two categories of the tr ansfer types, the periodic and asynchronous transfer types. the periodic transfer type includes the isochronous and interrupt transfers, while the asynchronous transfer type includes the control and bulk transfers. the ehci host controller has schedule interface that provides to the separate schedules for each category of the transfer type. the periodic schedule is based on a time - oriented frame list that represents a slide window of time of the host controller work items. all the iso and int transfers are serviced via the periodic schedule. the asynchronous schedule is a simple circular list of the schedule work items that provides a round robin service opportunity for all the asynchronous transfers. the ehci host c ontroller contains the isochronous transfer descriptor (itd), queue head (qh) and queue element transfer descriptor (qtd), and split transaction isochronous transfer descriptor (sitd) data structure interface to support the isochronous/interrupt/control/bu lk transfers and split transaction. the ehci host controller internal buffer memory is 24kb. start_addr_mem register is allocated from 0x0000 to 0x5fff. 4.8 system clock 4.8.1 phase locked loop (pll) clock multiplier the internal pll supports 12mhz, 19.2mhz, or 24mhz input, which can be crystal or a clock already existing in system. the frequency selection can be done using the freqsel1 and freqsel2 pins. table 4.3 provides clock frequency selection. freqsel1 freqsel2 clock frequency 0 0 12mhz 1 0 19.2mhz 0 1 24mhz table 4 - 3 clock frequency select
copyright ? 201 3 future technology devices international limited 18 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 4.9 power manage ment 4.9.1 power up and reset sequence when vcc(i/o) and vcc(3v3) are on, an internal r egulator will power on with vcc(3v3) on. a n internal por pulse will be generated during the regulator power on, so that internal circuits are in reset state until the regulator power is stable. 4.9.2 power supply power supplies are defined in table 4.4 . symbol typical description vcc(i/o) 1.8v, or 2.5v, or 3.3v supply for digital i/o pad vcc(3v3) 3.3v supply for chip table 4 - 4 power supply 4.9.3 atx reference voltage the atx circuit provides a stable internal voltage reference (+1.2v) to bias the analog circuitry. this circuit requires an accurate external reference resistor. connect 12 k ?1% resistor between pins rref and gnd. 4.9.4 power modes power management configuration defined in table 4.5. for each bit description, see config register. osc_en pll_en hc_clk_en description 1 1 1 operation mode 0 0 0 suspend mode table 4 - 5 power management configuration 4.9.4.1 operation mode all power supplies are present. host controller is active. 4.9.4.2 suspend mode all power supplies are present. host controller goes to u sb suspend. the steps for the host suspend are as follows: 1. clear the rs bi t of the usbcmd register to stop the host controller from executing schedule. 2. set the po_susp bit of the portsc register to force the host controller to go into suspend. 3. d isab le osc_en, pll_en and hc_clk_en bits of the config register to save power. 4. clear the u_susp_u bit of the eottime register to put the chip into suspend mode.
copyright ? 201 3 future technology devices international limited 19 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 4.9.4.3 wake up the regulator will be in normal operating mode and the clock /oscillator/pll will be enabled when either of these conditions is triggered: 1. dummy read access with a low pulse on pins cs_n/ce_n and rd_n /re_n/oe_n. 2. usb device connects or disconnects. 3. remote wake up from external usb device. 4. over current condition is triggered on oc_n if enable d by register . after wake up automatically set corresponding bit of the config register, must set the u_susp_u bit of the eottime register to wake up the chip . 4.10 bcd mode the ft313h is a n ehci - compatible host controller with bcd block function , which follows the battery charging specification revision 1.2(bc1. 2) by usb - if. the block function that emulates usb host port as either charging downstream port (cdp) or de dicated charging port (dcp) which provides higher current sourc e than standard downstream port (sdp). the bcd logic block will decode the mode of operation and choose by following setting : 1. bcd function is default enable by config register bit[5] setting . 2. bcd mode selection is default controlled by external pins configuration. set config register bit[ 1 5] to take over bcd mode setting by software. 3. same configuration by config register bit[14:13] to set bcd mode if software take s over control. cpe1 cpe0 mode bcd_en description 0 0 sdp 1 standard downstream port, vbus current limit 500ma 0 1 dcp 1 dedicated charging port, usb host no functional on this port, vbus current limit 1.5a 1 1 cdp 1 charging downstream port alternative configuration, vbus current limit 1.5a x x x 0 bcd function disable table 4 - 6 bcd mode configuration
copyright ? 201 3 future technology devices international limited 20 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 5 host controller specific registers 5.1 overview of registers table 5.1 shows the definitions of the ft313h host controller specific registers. address register reset value description ehci operational register 00h hc caplength 0100 0010 h capability register 04h hcsparams 0000 0001 h structural parameter register 08h hccparams 0000 0006 h capability parameter register 10h usbcmd 0008 0b00 h usb command register 14h usbsts 0000 1000 h usb status register 18h usbintr 0000 0000 h usb interrupt enable register 1ch frindex 0000 0000 h frame index register 24h periodiclistaddr 0000 0000 h periodic frame list base address register 28h asynclistaddr 0000 0000 h current asynchronous list address register 30h postsc 0000 0000 h port status and control register configuration register 34h eoftime 0000 0041 h eof time and asynchronous schedule sleep timer register 80h chipid 0 313 0 0 0 1 h chip id register 84h hwmode 0000 0000 h hw mode control register 88h edgeintc 0000 00 1 f h edge interrupt control register 8ch swreset 0000 0000 h sw reset register 90h memaddr 0000 h memory address register 92h dataport 0000 h data port register 94h datasession 0000 h data session length register 96h config 1fa0 h configuration register 98h aux_ memaddr 0000 h auxiliary memory address register 9ah aux_ dataport 0000 h auxiliary data port register 9ch sleeptimer 0400 h sleep timer register interrupt register a0h hcintsts 0000 h host controller interrupt status register
copyright ? 201 3 future technology devices international limited 21 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 address register reset value description a4h hcinten 0000 h host controller interrupt enable register usb testing register 50h testmode 0000 0000 h test mode register 70h testpmset1 0000 0000 h test parameter setting 1 register 74h testpmset2 0000 0000 h test parameter setting 2 register table 5 - 1 overview of host controller specific registers 5.2 ehci operational registers 5.2.1 hc caplength register (address = 00h) this register is used as an offset to add to register base to find the beginning of the operational register space. the high two bytes contain a bcd encoding of the ehci revision number supported by this host controller. the most signification byte of this register represents a m ajor revision and the least significat ion byte is the minor revision. bit name type default value description [31:16] hciversion ro 16h0100 host controller interface version number this register is a 2 - byte register containing a bcd encoding of the ehci revision number supported by the host controller. [15:8] reserved ro 8h0 8h10 capability register length this register is used as an o ffset added to register base to find out the beginning of the operational register space. table 5 - 2 capability register 5.2.2 hcsparams register (address = 04h) this is a set of fields that are structural parameter: number of downstream ports, etc . bit name type default value description [31:4] reserved ro 28h0 4h1 number of ports this field specifies the number of the physical downstream ports implemented on the host controller. table 5 - 3 structural parameter register
copyright ? 201 3 future technology devices international limited 22 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 5.2.3 hccparams register (address = 08h) this is multiple mode control (time base bit functionality) and addressing capability. bit name type default value description [31:3] reserved ro 29h0 1b1 asynchronous schedule park capability the host controller supports the park feature for high - speed queue heads in the asynchronous schedule. this feature can be disabled or enabled and set to a specific level by using the asynchronous schedule park mode enable and asynchronous schedule park mode count fields in the usbcmd register. 1 pflf ro 1b1 programmable frame list flag when this bit is set to 1b, the system software can specify and use a smaller frame list and configure the host controller via frame list size field of the usbcmd register. this requirement ensures that the frame list is always physically contiguous. 0 reserved ro 1b0 table 5 - 4 c apability parameter register 5.2.4 usbcmd register (address = 10h) the command register indicates the command to be executed by the serial bus host controller. writing to the register causes a command to be executed. bit name type default value description [31:24] reserved ro 8h0 8h08 interrupt threshold control this field is used by the system software to select the maximum rate at which the host controller will issue the interrupts. the only valid values are described as below: value max interrupt interval for the high - speed 00h reserved 01h no limited interval 02h 2 micro - frames 04h 4 micro - frames 08h 8 micro - frames (default, equals to 1 ms) 10h 16 micro - frames (2 ms) 20h 32 micro - frames (4 ms) 40h 64 micro - frames (8 ms)
copyright ? 201 3 future technology devices international limited 23 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description note 1 : this is further gated by min_width bits of edgeintc register if edge trigger interrupt is used. note2: in the full - speed mode, these registers are reserved. [15:12] reserved ro 4 b0 1b1 asynchronous schedule park mode enable software uses this register to enable or disable the park mode. when this register is set to 1, 1b0 2b11 asynchronous schedule park mode count this field contains a count for the number of successive transactions that the host controller is allowed to execute from a high - speed queue head on the asynchronous schedule. 7 reserved ro 1b0 1b0 interrupt on asynchronous advance doorbell this bit is used as a doorbell by software to ring the host controller to issue an interrupt at the next advance of the asynchronous schedule. 5 asch_en r/w 1b0 asynchronous schedule enable this bit controls whether the host controller skips the processing of asynchronous schedule. 0: do not process the asynchronous schedule 1: use the asynclistaddr register to access the asynchronous schedule 4 psch_en r/w 1b0 periodic schedule enable this bit controls whether the host controller skips the processing of the periodic schedule. 0: do not process the periodic schedule 1: use the periodickistbase register to access the periodic schedule [3:2] frl_size r/w 2b00 frame list size this field specifies the size of the frame list. 00: 1024 elements (4096 bytes; default value) 01: 512 elements (2048 bytes) 10: 256 elements (1024 bytes) 11: reserved 1 hc_reset r/w 1b0 host controller reset this control bit is used by the software to reset the host controller.
copyright ? 201 3 future technology devices international limited 24 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description 0 rs r/w 1b0 run/stop when this bit is set to 1b, the host controller proceeds with the execution of schedule. 0: stop 1: run table 5 - 5 usb command register 5.2.5 usbsts register (address = 14h) this register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register . software sets a bit to 0 in this register by writing a 1 to it. bit name type default value description [31: 16 ] reserved ro 16 h0 1b0 asynchronous schedule status this bit reports the actual status of the asynchronous schedule. 14 psch_sts ro 1b0 periodic schedule status this bit reports the actual status of the periodic schedule. 13 reclamation ro 1b0 reclamation this is a read - only status bit, and used to detect an empty of the asynchronous schedule. 12 hchalted ro 1 host controller halted this bit is a zero whenever the run/stop bit is set to 1. the host controller sets this bit to 1 b0 1b0 interrupt on asynchronous advance this status bit indicates the assertion of interrupt on async advance doorbell . 4 h_syserr r/wc 1b0 host system error the host controller sets this bit to 1 when a 1b0 frame list rollover the host controller sets this bit to 1 when the frame list index rolls over from its maximum value to zero. 2 po_chg_det r/wc 1b0 port change detect the host controller sets this bit to 1 when any change bit transition from 0 to 1.
copyright ? 201 3 future technology devices international limited 25 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description the portsc change bits. 1 usberr_int r/wc 1b0 usb error interrupt the host controller sets this bit to 1 when the 1b0 usb interrupt the host controller sets this bit to 1 upon the table 5 - 6 usb status register 5.2.6 usbintr register (address = 18h) this register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that are disabled in this register still appear in the usbsts to allow the software to poll for events. bit name type default value description [31:6] reserved ro 26h0 1b0 interrupt on async advance enable when this bit is set to 1, and the interrupt on async advance bit in the usbsts register is set to 1 also, the 1b0 host system error enable when this bit is set to 1, and the host system error status bit in the usbsts register is set to 1 also, the host 1b0 frame list rollover enable when this bit is set to 1, and the frame list rollover bit in the usbsts register is set to 1 2 po_chg_det_en r/w 1b0 port change interrupt enable when this bit is set to 1, and the port change detect bit in the usbsts register is set to 1 1b0 usb error interrupt enable when this bit is set to 1, and the usberrint usbsts register is set to 1 also, the 1b0 usb interrupt enable when this bit is set to 1, and the usbint bit egister is a set to 1 also, the table 5 - 7 usb i nterrupt enable register
copyright ? 201 3 future technology devices international limited 26 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 5.2.7 frindex register (address = 1ch) this register is used by the host controller to index into the periodic frame . the register updates very 125 microseconds (one each micro - frame). bit name type default value description [31:14 ] reserved ro 28 h0 b0 frame index this register is used by the host controller to index the frame into the periodic frame list. it updates every 125 microseconds. this register cannot be written unless the host controller is at the halted state. bits[n:3] are used for frame list current index. this means that each location of the frame list is accessed 8 times before moving to the next index. usbcmd[frame list size] number elements n 00b (1024) 12 01b (512) 11 10b (256) 10 11b reserved table 5 - 8 frame index register 5.2.8 periodiclistaddr register (address = 24h) this 32 - bit register contains the beginning address of the periodic frame list in the system memory. bit name type default value description [31:12] peri_baseadr r/w 20h0 periodic frame list base address this 32 - bit register contains the beginning address of the periodic frame list in the system memory. these bits correspond to the memory address signals[31:12]. [11:0] reserved ro 12b0 table 5 - 9 periodic frame list base address register 5.2.9 asynclistaddr register (address = 28h) this 32 - bit register contains the address of the next asynchronous queue head to be executed . bit name type default value description [31:5 ] async_ladr r/w 27h0 current asynchronous list address this 32 - bit register contains the address of the next asynchronous queue head to be executed. these bits correspond to the m emory address signal s [31:5]. [ 4 :0] reserved ro 5 b0 table 5 - 10 current asynchronous list address register
copyright ? 201 3 future technology devices international limited 27 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 5.2.10 postsc register (address = 30h) the port status and control register is in the power well . it is only reset by hardware when the power is initially applied or in response to a host controller reset. the initial conditions of a port are: ? no peripheral connected ? port disable the software must not attempt to change the state of the port until the power is stable on the port. the host is required to have power stable to the port within 20 milliseconds of the zero to one transition. when a peripheral device is attached, the port state transitions to the connected state and system software will proces s this as with any status change notification. bit name type default value description [31:17 ] reserved ro 15 h0 1b0 test force enable when thi s signal is written as 1, the b0 2b00 line status these bits reflect the current logical levels of the d+ and d - signal lines. bits[11:10] usb state 00b se0 10b j - state 01b k - state 11b undefined 9 reserved ro 1b0 1b0 port reset 1 = port is in the reset state. 0 = port is not in the reset state. when the software writes a 1 to this bit, the software writes a 0 to this bit to terminate the at a 1 long enough to note: reset signal which shall be follow ed by the usb2.0 chapter 7.1.7.5 reset signal requirement. if detected hs device, the software shall wait more than 200us for port reset clearing . before setting this bit, run/stop bit should be set to 0. 1b0 port suspend 1 = port is in the suspend state 0 = port is not in the suspend state.
copyright ? 201 3 future technology devices international limited 28 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description the port enable bit and suspend bit of this register define the port state as follows: bits[port enable, suspend] port state 0x disable 10 enable 11 suspend at th e suspend state, the downstream propagation of the data is blocked on this port, except for the port reset. while at the suspend state, the port is sensitive to resume detection. writing a 0 to this bit is ignored by the unconditionally set this bit to a 0 when: the software sets force port resume bit to a 0 the software sets port reset bit to a 1 (from a 0) 1b0 force port resume 1 = resume detected/driven on port. 0 = no resume detected/driven on port. software s ets this bit to a 1 to resume signal the host controller sets this bit to a 1 if a j a 1 for to a 1. 2b0 1b0 port enable/disable change 1 = port enable/disable status has changed. 0 = no change 2 po_en r/w 1b0 port enable/disable 1 = enable 0 = disable ports can only be enabled by the host controller as a part of the reset and enable. software cannot enable a port by writing a one to this field. 1 conn_chg r/wc 1b0 connect status change 1 = change current connect status 0 = no change. this bit indicates a change has occurred in the current connect status of the port. 0 conn_sts ro 1b0 current connect status 1 = device is presented on the port. 0 = no device is presented.
copyright ? 201 3 future technology devices international limited 29 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description this value reflects the current state of the port, and may not correspond directly to cause the connect status change bit to be set. table 5 - 11 port status and control register 5.3 configuration registers 5.3.1 eottime register (address = 34h) bit name type default value description [31:7] reserved ro 25 h 0 - 6 u_susp_n r/w 1b1 transceiver suspend mode active low places the transceiver in the suspend mode that draws the minimal power from the power supplies. this is part of the power m anagement. [5:4] eof2_time r/w 2b0 0 eof 2 timing points control eof2 timing point before next sof. high - speed eof2 time 00b 2 clocks (30 mhz) = 66 ns 01b 4 clocks (30 mhz) = 133 ns 10b 8 clocks (30 mhz) = 266 ns 11b 16 clocks (30 mhz) = 533 ns full - speed eof2 time 00b 20 clocks (30 mhz)=8 clocks (12 mhz) = 666 ns 01b 40 clocks (30 mhz)=16 clocks (12 mhz) = 1.333 s 10b 80 clocks (30 mhz) = 32 clocks (12 mhz) = 2.66 s 11b 160 clocks (30 mhz) = 64 clocks (12 mhz) = 5.3 s low - speed eof2 time 00b 40 clocks (30 mhz) = 16 clocks (12 mhz) = 1.33 s 01b 80 clocks (30 mhz) = 32 clocks (12 mhz) = 2.66 s 10b 160 clocks (30 mhz) = 64 clocks (12 mhz) = 5.33 s 11b 320 clocks (30 mhz) = 128 clocks (12 mhz) = 10.66 s [3:2] eof1_time r/w 2b0 0 eof 1 timing points c ontrols the eof1 timing point before next sof. this value should be adjusted according to the maximum packet size. high - speed eof1 time 00b 540 clocks (30 mhz) = 18 s 01b 360 clocks (30 mhz) = 12 s 10b 180 clocks (30 mhz) = 6 s 11b 720 clocks (30 mhz) = 24 s full - speed eof1 time 00b 1600 clocks (30 mhz) = 640 clocks (12 mhz) = 53.3 s 01b 1400 clocks (30 mhz) = 560 clocks (12 mhz) = 46.6 s 10b 1200 clocks (30 mhz) = 480 clocks (12 mhz) = 40 s 11b 21000 clocks (30 mhz) = 8400 clocks (12 mhz)=700 s low - speed eof1 time
copyright ? 201 3 future technology devices international limited 30 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description 00b 3750 clocks (30 mhz) = 1500 clocks (12 mhz) = 125 s 01b 3500 clocks (30 mhz) = 1400 clocks (12 mhz) = 116 s 10b 3250 clocks (30 mhz) = 1300 clocks (12 mhz) = 108 s 11b 4000 clocks (30 mhz) = 1600 clocks (12 mhz) = 133 s [1:0] asyn_sch_slpt r/w 2b0 asynchronous schedule sleep timer controls the asynchronous schedule sleep timer. 00b 5 s 01b 10 s 10b 15 s 11b 20 s table 5 - 12 eof time and asynchronous schedule sleep timer register 5.3.2 chipid register (address = 80h) this chip id register contains the chip identification and hardware version numbers. bit name type default value description [31:0] chip_id ro 32h c hip id table 5 - 13 chip id register 5.3.3 hwmode register (address = 84h) bit name type default value description [15: 8] reserved ro 8b0 - [7: 6] host_spd_typ ro 2b00 host speed type indicate the speed type of attached device 2b10: hs 2b00: fs 2b01: ls 2b11: reserved 5 dack_pol r/w 1b0 dack polarity 0: active low 1: active high 4 dreq_pol r/w 1b0 dreq polarity 0: active low 1: active high 3 intf_lock r/w 1b0 interface lock 0: unlock the bus interface 1: lock the bus interface
copyright ? 201 3 future technology devices international limited 31 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description 2 intr_pol r/w 1b0 interrupt polarity 0: active low 1: active high 1 intr_level r/w 1b0 interrupt level 0: level trigger 1: edge trigged . the pulse width depends on the no_of_clk bits in the edgeintc register. 0 global_intr_en r/w 1b0 globe interrupt enable 0 : int assertion disabled . int will never be asserted, regardless of other settings or int events. 1 : int assertion enabled . int will be asserted according to the hcinten register, and event setting and occurrence. table 5 - 14 hw mode register 5.3.4 e dgeintc register (address = 88h) bit name type default value description [31:24] min_width r/w 8b0 minimum interval indicates the minimum interval between two edge interrupts in usofs (1 usof = 125us). this is not valid for level interrupts. a count of zero means that an interrupt occurs as when an event occurs. [23:16] reserved ro 8b0 - [15: 0] no_of_clk r/w 16b1f number of clocks number of clocks that an edge interrupt must be kept asserted on the interface. the default int pulse width is approximately 500ns. (n+1)*60mhz system clock. table 5 - 15 edge interrupt control registe r 5.3.5 swreset register (address = 8ch) bit name type default value description [15: 8] reserved ro 8b0 - [7: 6] intf_mode ro 2b00 interface mode 00b: reserved 01b: generic multiplex mode
copyright ? 201 3 future technology devices international limited 32 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description 10b: nor mode 11b: sram mode write to these bits have no effect. 5 reserved ro 1b0 - 4 data_bus_width r/w 1b0 data bus width 0: defines a 16 - bit data bus width. 1: sets a 8 - bit data bus width. 3 reserved ro 1b0 - 2 reset_atx r/w 1b0 reset usb transceiver 0: no reset 1: enable reset when the software writes a 1 to this 1b0 reset host controller 0: no reset 1: enable reset when the software writes a 1 to this 1b0 reset all system 0: no reset 1: enable reset when the software writes a 1 to this table 5 - 16 sw reset register
copyright ? 201 3 future technology devices international limited 33 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 5.3.6 memaddr register (address = 90h) bit name type default value description [15: 0] start_addr_mem r/w 16b0 start address for memory read / write internal 24k ram memory address from 0x0000 to 0x5fff. used by pio and dma. table 5 - 17 memory address register 5.3.7 dataport register (address = 92h) bit name type default value description [15: 0] data_port r/w 16b0 data port read / write data from / to memory must go through this port. used by pio and dma. table 5 - 18 data port register 5.3.8 datasession register (address = 94h) bit name type default value description 15 mem_rw r/w 1b0 memory read or write 0: w rite data into memory 1: read data from memory used by pio and dma [14: 0] data_len r/w 15b0 data length for memory read or write prese t the data length for memory read/write. the max data length is 24k. used by pio and dma table 5 - 19 d ata session le n gth register 5.3.9 config register (address = 96 h) bit name type default value description 1 5 bcd_mode_ ctrl r/w 1b0 bcd mode override control 0: external cpe0 and cpe1 pins configuration take effect. 1: bcd_m ode [ 1:0] register bits take effect [14:13] bcd_mode [1:0] r/w 2b00 bcd mode setting 00: sdp standard downstream po rt, vbus current limit 500ma. 01: dcp
copyright ? 201 3 future technology devices international limited 34 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description dedicated charging port . usb host not functional on this port, vbus current limit 1b 1b1 oscillator enable 0: oscillator is not active 1: oscillator is active 10 pll_en r/w 1b1 internal pll enable 0: pll is disable 1: pll is enable 9 reserved - 1b1 - 8 hc_clk_en r/w 1b1 host controller clock enable 0: clocks are disabled 1: clocks are enabled 7 vbus_off r/w 1b vbus power switch this bit controls the voltage o n the vbus on/off (default is 1 1b0 port overcurrent enable 0: disable over current detection 1: enable over current detection 5 bcd_en r/w 1b1 bcd module enable 0: disable bcd module 1: enable bcd module 4 reserved r o 1 b0 - [3: 2] burst_len r/w 2b00 dma burst length 00 : single dma burst 01 : 4 - cycle dma burst 10 : 8 - cycle dma burst 11 : 16 - cycle dma burst 1 enable_dma r/w 1b0 enable dma 0: terminate dma
copyright ? 201 3 future technology devices international limited 35 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description 1: enable dma 0 dma_abort r/w 1'b0 dma abort 0: dma continuous running 1: dma abort implement table 5 - 20 dma configuration register 5.3.10 aux_ memaddr register (address = 98h) bit name type default value description [15: 0] aux_ start_addr_mem r/w 16b0 auxiliary start address of memory read / write when memory is occurred by dma, use auxiliary start address for pio memory access. table 5 - 21 aux memory address register 5.3.11 aux_dataport register (address = 9ah) bit name type default value description [15: 0] aux_data_port r/w 16b0 auxiliary data port when memory is occurred by dma, use auxiliary data port for pio memory access. table 5 - 22 aux data port register 5.3.12 sleeptimer register (address = 9ch) bit name type default value description [15: 0] sleep_timer r/w 16b0400 sleep timer when host controller detected usb bus has no activity, the sleep timer will be started. when timer reduce to zero , the busin active interrupt will be generated, if the respective enable bit in the hcinten r egister is set. default sleep timer is app roximatel y 10ms. table 5 - 23 sleep timer register 5.4 interrupt registers 5.4.1 hcintsts register (address = a0h) bit name type default value description [15: 8 ] reserved ro 1 0 b0 - 7 wakeupint r/wc 1b0 wake up interrupt on device connect or
copyright ? 201 3 future technology devices international limited 36 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description disconnect indicates that wake up event is triggered. the int line will be asserted if the respective enable bit in the hcinten register is set. 0: no wake up event has occurred on the port when device connects or disconnects. 1: wake up event has occurred on the port when device connects or disconnects. 6 ocint r/wc 1b0 overcurrent interrupt indicates that overcurrent event is triggered. the int line will be asserted if the respective enable bit in the hcinten register is set. 0: no overcurrent event has occurred. 1: overcurrent event has occurred. 5 clkready r/w c 1b0 1b0 usb bus inactive interrupt indicates that usb bus is inactive. the int line will be asserted if the respective enable bit in the hcinten register is set. 0: usb bus is active . 1: usb bus is inactive. 3 remotewkint r/w c 1b0 remote wake up interrupt indicates int was generated when the host controller remote wakeup . the int line will be asserted if the respective enable bit in the hcinten register is set. 0: no remote wake up. 1: remote wake up event occurred. 2 dmaeotint r/w c 1b0 dma eot interrupt indicates the dma transfer completion. the int line will be asser ted if the respective enable bit in the hcinten register is set. 0: no dma transfer is completed. 1: dma transfer is completed. 1 sofint r/w c 1b0 sof interrupt the int line will be asserted if the respective bit enable is set.
copyright ? 201 3 future technology devices international limited 37 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description 0: no sof event has occurred. 1: sof event has occurred. 0 msofint r/w c 1b0 usof interrupt the int line will be asserted if the respective enable bit in the hcinten register is set. 0: no usof event has occurred. 1: usof event has occurred. table 5 - 24 hc interrupt status register 5.4.2 hcinten register (address = a4h) bit name type default value description [15: 8 ] reserved ro 1 0 b0 - 7 wakeupint_en r/w 1b0 wake up interrupt enable on device connect or disconnect control the int generation when the device connects or disconnects as wake up events. 0: no int will be generated when device connects or disconnects as wake up events. 1: int will be asserted when device connects or disconnects as wake up events. 6 ocint_en r/w 1b0 overcurrent interrupt enable control the int generation when the overcurrent event triggers 0: no int will be generated after overcurrent event is triggered. 1: int will be asserted after overcurrent event is triggered. 5 clkready _en r/w 1b0 clock ready enable control the int generation when the internal clock signals are running stable 0: no int will be generated after clock runs stable . 1: int will be asserted after clock runs stable. 4 businactive_en r/w 1b0 usb bus inactive enable control the int generation when the usb bus is inactive 0: no int will be generated when the usb bus is inactive. 1: int will be asserted when the usb bus is inactive. 3 r/w 1b0 r emote wake up interrupt enable
copyright ? 201 3 future technology devices international limited 38 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description remotewkint _en control the int generation when the host controller supports remote wake up 0: no int will be generated when remote wake up occurred. 1: int will be asserted when remote wake up occurred. 2 dmaeotint_en r/w 1b0 dma eot interrupt enable control assertion of int on the dma transfer completion 0: no int will be generated when a dma transfer is completed. 1: int will be asserted when a dma transfer is completed. 1 sofint_en r/w 1b0 sof interrupt enable co ntrol the int generation at every sof occurrence 0: no int will be generated on sof. 1: int will be asserted at every sof. 0 msofint_en r/w 1b0 usof interrupt enable control the int generation at every usof occurrence 0: no int will be generated on usof . 1: int will be asserted at every usof. table 5 - 25 hc interrupt status register 5.5 usb testing registers 5.5.1 testmode register (address = 50h) this register allows the firmware to set the dp and dm pins to predetermined states for testing purposes. once force one test mode on host, must use test device on port connection. note: only one bit can be set to logic 1 at a time. after writing to this register, need add 150ns delay before writing this register again. the registers 70h and 74h both have same operation. bit name type default value description [31:5] reserved ro 27b0 1b0 set to 1, the host controller will enter the loop 1b0 1b0 test_packet after entering the high speed and writing 1b1
copyright ? 201 3 future technology devices international limited 39 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 bit name type default value description in the usb2.0 spe cification from the memory to fifo. then, send the packet to the transceiver. 1 tst_ksta r/w 1b0 test_k upon writing a 1, the d+/d 1b0 test_j upon writing a 1, the d+/d table 5 - 26 test mode register 5.5.2 testpmset1 register (address = 70h) this parameter setting register is only used by test packet mode. bit name type default value description [31:25] reserved ro 7b0 11h dma length the total bytes of the dma controller will move. the maximum length is 1024 C 6b0 1b0 dma type the transfer type of data moving 0: fifo to memory 1: memory to fifo 0 dma_start r/w 1b0 dma start this bit informs the dma controller to initiate the dma transfer. table 5 - 27 test mode parameter setting 1 register 5.5.3 testpmset2 register (address = 74h) this parameter setting register is only used by test packet mode. bit name type default value description [31:0] dma_maddr r/w 32b0 table 5 - 28 test parameter setting 2 register
copyright ? 201 3 future technology devices international limited 40 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 6 devices characteristics and ratings 6.1 absolute maximum ratings the absolute maximum ratings for the ft313h device are as follows. these are in accordance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device. parameter value unit storage temperature - 65c to 150c degrees c floor life (out of bag) at factory ambient (30c / 60% relative humidity) 168 hours (ipc/jedec j - std - 033a msl level 3 compliant)* hours ambient temperature (power applied) - 40c to 85c degrees c vcc supply voltage 0 to + 5 v vcc(i/o) supply voltage 0 to + 5 v dc input voltage C v dc input voltage C C v table 6 - 1 absolute maximum ratings * if devices are stored out of the packaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of + 125 c and baked for up to 17 hours .
copyright ? 201 3 future technology devices international limited 41 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 6.2 dc characteristics dc characteristics (ambient temperature = - 40c to + 85c ) parameter description minimum typical maximum units conditions vcc(i/o) vcc io o perating s upply v oltage 1.62 1.8 1.98 v normal operation 2.25 2.5 2.75 v 2.97 3.3 3.63 v vcc (3v3) vcc o perating s upply v oltage 2.97 3.3 3.63 v normal operation icc1 idle current - 20 - ma idle icc 2 operating c urrent - 35 - ma normal operation high speed data transfer icc 3 usb suspend - 200 - ua usb suspend v cc (1v2) core s upply v oltage 1.08 1.2 1.32 v normal operation vout(1v2) internal 1.2v regulator voltage - 1.2 - v normal operation table 6 - 2 operating voltage and current parameter description minimum typical maximum units conditions voh output voltage high 2.4 3.3 - v ioh= 8ma vol output voltage low - - 0.4 v iol= 8ma vi h input high voltage 2 .0 - - v - v il input low voltage - - 0.8 v - vth schmitt hysteresis voltage 0.3 0.45 0.5 v - ipu input pull - up current 25 42 60 ua vin = 0 v rpu input pull - up resistance equivalent 120k 78k 60k ohm vin = 0 v ipd input pull - down current 25 42 60 ua vin = vcc(i/o) rpd input pull - down resistance equivalent 120k 78k 60k ohm vin = vcc(i/o) iin input leakage current - 10 1 10 ua vin = vcc(i/o) or 0 ioz tri - state output leakage current - 10 1 10 ua - table 6 - 3 digital i/o pin characteristics (vcc(i/o) = +3.3v, standard drive level)
copyright ? 201 3 future technology devices international limited 42 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 parameter description minimum typical maximum units conditions voh output voltage high vcc(i/o) - 0.4 2.5 - v ioh= 6ma vol output voltage low - - 0.4 v iol= 6ma vi h input high voltage 0.7 vcc(i/o) - - v - v il input low voltage - - 0.3 vcc(i/o) v - vth schmitt hysteresis voltage 0.28 0.39 0.5 v - ipu input pull - up current 14 23 35 ua vin = 0 rpu input pull - up resistance equivalent 160k 108k 78k ohm vin = 0 ipd input pull - down current 14 23 35 ua vin = vcc(i/o) rpd input pull - down resistance equivalent 160k 108k 78k ohm vin = vcc(i/o) iin input leakage current - 10 1 10 ua vin = vcc(i/o) or 0 ioz tri - state output leakage current - 10 1 10 ua - table 6 - 4 digital i/o pin characteristics (vcc(i/o) = +2.5v, standard drive level) parameter description minimum typical maximum units conditions voh output voltage high vcc(i/o) - 0.4 1.8 - v ioh= 3.6ma vol output voltage low - - 0.4 v iol= 3.6ma vi h input high voltage 0.7vcc(i/o) - - v - v il input low voltage - - 0.3 vcc(i/o) v - vth schmitt hysteresis voltage 0.25 0.35 0.5 v - ipu input pull - up current 6 10 15 ua vin = 0 rpu input pull - up resistance equivalent 270k 180k 130k ohm vin = 0 ipd input pull - down current 6 10 15 ua vin = vcc(i/o) rpd input pull - down resistance equivalent 270k 180k 130k ohm vin = vcc(i/o) iin input leakage current - 10 1 10 ua vin = vcc(i/o) or 0 ioz tri - state output leakage current - 10 1 10 ua - table 6 - 5 digital i/o pin characteristics (vcc( i/o) = +1.8v, standard drive level)
copyright ? 201 3 future technology devices international limited 43 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 parameter description minimum typical maximum units conditions input level for high speed vhscm voltage of high speed data signal in the common mode - 50 - 500 mv - vhssq high speed squelch detection threshold - - 100 mv squelch is detected 150 - - mv squelch is not detected vhsdsc high speed disconnection detection threshold 625 - - mv disconnection is detected - - 525 mv disconnection is not detected output level for high speed vhsoi high speed idle output voltage (differential) - 10 - 10 mv - vhsol high speed low level output voltage (differential) - 10 - 10 mv - vhsoh high speed high level output voltage (differential) - 360 - 400 mv - vchirpj chirp - j output voltage (differential) 700 - 1100 mv - vchirpk chirp - k output voltage (differential) - 900 - - 500 mv - input level for full speed and low speed vdi differential input voltage sensitivity 0.2 - - v |vdp - vdm| vcm differential common mode voltage 0.8 - 2.5 v - vse single ended receiver threshold 0.8 - 2.0 v - output level for full speed and low speed vol low level output voltage 0 - 0.3 v - voh high level output voltage 2.8 - 3.6 v - resistance
copyright ? 201 3 future technology devices international limited 44 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 parameter description minimum typical maximum units conditions rdrv driver output impedance 40.5 45 49.5 ohm equivalent resistance used as an internal chip table 6 - 6 usb i/o pin (usbdp, usbdm) characteristics parameter description minimum typical maximum units conditions voh output voltage high 2.4 - - v ioh= 2ma~16 ma vol output voltage low - - 0.4 v iol= 2ma~16ma vi h input high voltage 2.0 - - v lvttl v il input low voltage - - 0.8 v lvttl vopu * output pull up voltage for 5v toleran t i/os vcc(3v3) - 0.9 - - v ipu = 1ua iin input leakage current - 1 - ua vin = vcc(3v3) or 0 - 1 - ua vin = 5v or 0 cin input capacitor - 2.3 - pf vcc(3v3) with 5v toleran t i/o table 6 - 7 5v t olerant pin (psw_n, oc_n , vbus ) characteristics note*: this parameter is to indicate that the pull up resistor for the 5v toleran t i/os cannot reach vcc(3v3) dc level even without dc loading current. 6.3 ac characteristics ac characteristics (ambient temperature = - 40c to + 85c ) system clock dynamic characteristics: parameter value unit minimum typical maximum crystal oscillator clock frequency - 12.00 - mhz - 19.2 0 - - 24 .00 - external clock input external clock jitter - - 500 ps clock duty cycle 45 50 55 %
copyright ? 201 3 future technology devices international limited 45 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 input voltage on pin x1/clkin - 3.3 - v recommended accuracy of the clock frequency is 50ppm for the crystal. table 6 - 8 system clock characteristics analog i/o pins (dp/dm) dynamic characteristics: parameter description minimum typical maximum units conditions driver characteristic for high speed thsr high speed differential rise time 500 - - ps - thsf high speed differential fall time 500 - - ps - driver characteristic for full speed tfr rise time of dp/dm 4 - 20 ns cl=50pf 10%~90% of |voh C vol| tff fall time of dp/dm 4 - 20 ns cl=50pf 10%~90% of |voh C vol| tfrma differential rise/fall time matching 90 - 110 % the first transition exclude from the idle mode driver characteristic for low speed tlr rise time of dp/dm 75 - 300 ns cl=200pf~600pf 10%~90% of |voh C vol| tlf fall time of dp/dm 75 - 300 ns cl=200pf~600pf 10%~90% of |voh C vol| tlrma differential rise/fall time matching 80 - 125 % the first transition exclude from the idle mode table 6 - 9 analog i/o pins characteristics
copyright ? 201 3 future technology devices international limited 46 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 6.4 timing 6.4.1 pio timing sram pio timing characteristics (ambient temperature = - 40c to + 85c ) parameter description v cc( i / o ) =1.8v vcc(i/o)=2.5v vcc(i/o)=3.3v unit min max min max min max tcs cs_n setup time before wr_n / rd_n low 0 - 0 - 0 - ns tch cs_n hold time after wr_n / rd_n high 0 - 0 - 0 - ns tcp cs_n pulse width for read 40 - 40 - 40 - ns cs_n pulse width for write 40 - 40 - 40 - ns tasrw address setup time before wr_n / rd_n low 0 - 0 - 0 - ns tahrw address hold time after wr_n/rd_n low 0 - 0 - 0 - ns tap address latch pulse width ns twc write cycle time 80 - 79 - 7 8.5 - ns twp wr_n pulse width 40 - 40 - 40 - ns tdh rd_n high to output hi - z 4 9 4 7 4 6 ns wr_n high to input hi - z 0 - 0 - 0 - ns tdadvh data setup time before data latch 6 - 6 - 6 - ns toe rd_n low to data output enable 8 - 7 - 6 - ns trp rd_n pulse width 40 - 40 - 40 - ns trc read cycle time 80 - 79.5 - 79 - ns table 6 - 10 sram pio timing
copyright ? 201 3 future technology devices international limited 47 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 figure 6 - 1 read in sram mode figure 6 - 2 write in sram mode t d h d a t a a d [ 1 5 : 0 ] a l e / a d v _ n r d _ n / r e _ n / o e _ n c s _ n / c e _ n w r _ n / w e _ n c l e t a h r w a d d r e s s a [ 7 : 0 ] t c s t c h t d a d v h t a s r w t r p t o e t c p t r c t d h d a t a a d [ 1 5 : 0 ] a l e / a d v _ n w r _ n / w e _ n c s _ n / c e _ n r d _ n / r e _ n / o e _ n c l e t a h r w a d d r e s s a [ 7 : 0 ] t c s t c h t d a d v h t a s r w t w p t c p t w c
copyright ? 201 3 future technology devices international limited 48 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 nor pio timing characteristics (ambient temperature = - 40c to + 85c ) parameter description vcc(i/o)=1.8v vcc(i/o)=2.5v vcc(i/o)=3.3v unit min max min max min max tch cs_n hold time after wr_n / rd_n high 0 - 0 - 0 - ns tcsadval cs_n setup time bef ore a ddress l atch 6.5 - 6.5 - 6 - ns tah address hold time after address latch 0 - 0 - 0 - ns tas address setup time before address latch 6 - 6 - 5 - ns tap address latch pulse width 10 - 10 - 10 - ns twc write cycle time 80 - 78.5 - 78.5 - ns twp wr_n pulse width 40 - 40 - 40 - ns tdh rd_n high to output hi - z 4 8 4 7 4 7 ns wr_n high to input hi - z 0 - 0 - 0 - ns tdadvh data setup time before data latch 6 - 5 - 5 - ns toe rd_n low to data output enable 8 - 6 - 5 - ns tbds ready to wr_n/rd_n low 5 - 5 - 5 - ns trp rd_n pulse width 40 - 40 - 40 - ns trc read cycle time 80 - 79 - 79 - ns table 6 - 11 nor pio timing
copyright ? 201 3 future technology devices international limited 49 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 figure 6 - 3 read in nor mode figure 6 - 4 write in nor mode t a s t a h t b d s t o e t d h a d d r e s s d a t a a d [ 1 5 : 0 ] a l e / a d v _ n r d _ n / r e _ n / o e _ n c s _ n / c e _ n w r _ n / w e _ n c l e t r c t c s a d v a l t a p t c h t r p t a s t a h t b d s t d a d v h t d h a d d r e s s d a t a a d [ 1 5 : 0 ] a l e / a d v _ n r d _ n / d s _ n / r e _ n / o e _ n c s _ n / c e _ n w r _ n / r w _ n / w e _ n c l e t w c t c s a d v a l t a p t c h t w p
copyright ? 201 3 future technology devices international limited 50 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 general multiplex pio timing characteristics (ambient temperature = - 40c to + 85c ) parameter description vcc(i/o)=1.8v vcc(i/o)=2.5v vcc(i/o)=3.3v unit min max min max min max tch cs_n hold time after wr_n / rd_n high 0 - 0 - 0 - ns tcsadval cs_n setup time before a ddress l atch 7.5 - 6.5 - 6.5 - ns tah address hold time after address latch 0 - 0 - 0 - ns tas address setup time before address latch 7 - 6 - 6 - ns tap address latch pulse width 10 - 10 - 10 - ns twc write cycle time 80 - 78.5 - 78.5 - ns twp wr_n pulse width 40 - 40 - 40 - ns tdh rd_n high to output hi - z 4 9 4 6.5 3.5 6 ns wr_n high to input hi - z 0 - 0 - 0 - ns tdadvh data setup time before data latch 6 .5 - 5 - 5 - ns toe rd_n low to data output enable 8 - 6 - 5 - ns tbds ready to wr_n/rd_n low 5 - 5 - 5 - ns trp rd_n pulse width 40 - 40 - 40 - ns trc read cycle time 80 - 79 - 79 - ns table 6 - 12 general multiplex pio timing
copyright ? 201 3 future technology devices international limited 51 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 figure 6 - 5 read in general multiplex mode figure 6 - 6 write in general multiplex mode t a s t a h t b d s t o e t d h a d d r e s s d a t a a d [ 1 5 : 0 ] a l e / a d v _ n r d _ n / r e _ n / o e _ n c s _ n / c e _ n w r _ n / w e _ n c l e t r c t c s a d v a l t a p t c h t r p t a s t a h t b d s t d a d v h t d h a d d r e s s d a t a a d [ 1 5 : 0 ] a l e / a d v _ n r d _ n / r e _ n / o e _ n c s _ n / c e _ n w r _ n / w e _ n c l e t w c t c s a d v a l t a p t c h t w p
copyright ? 201 3 future technology devices international limited 52 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 6.4.2 dma timing dma timing characteristics (ambient temperature = - 40c to + 85c ) parameter description min max unit t s udreqdack dreq set - up time before dack assertion 0 - ns t d dackdreq dack de - assertion to next dreq assertion time 18 - ns t h dreqdack dreq hold time after last strobe assertion - 35 ns t rwp rd_n/wr_n pulse width 40 - ns t oe data valid time after rd_n assertion 8 - ns t rdh read data hold time after rd_n de - asserts 4 9 ns t wdh write data hold time after wr_n de - assertion 0 - ns t dadvh write data set - up time before wr_n de - assertion 6 - ns t su dack rw dack set - up time before rd_n/wr_n assertion 0 - ns t rwdack dack de - assertion after rd_n/wr_n de - assertion 0 - ns t cy c dma read/write cycle time 80 - ns table 6 - 13 dma timing figure 6 - 7 dma read and write d r e q d a c k r d _ n / w r _ n d a t a [ 1 5 : 0 ] ( r e a d ) d a t a [ 1 5 : 0 ] ( w r i t e ) t s u d r e q d a c k t s u d a c k r w t r w p t c y c t h d r e q d a c k t d d a c k d r e q t r w d a c k t o e t r d h t d a d v h t w d h d a t a 1 d a t a 2 d a t a n
copyright ? 201 3 future technology devices international limited 53 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 7 application examples ft313h can be configured to communic ate with a microcontroller us es 16 - bit/8 - bit sram asynchronous bus interface, nor interface, and general multiplex interface. an example schematic is show in figure 7.1.
copyright ? 201 3 future technology devices international limited 54 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 figure 7 - 1 ft313h chip schematic 7.1 examples of bus interface connection 7.1.1 16 - bit sram a synchronous bus interface if dma transfer s are not used the dack and dreq signals may be left floating or the dack signal may be terminated with external 10 k ohm pull - down resistor . if the microcontroller has n o ad<0> pin for 16 - bit wide device s , the unused ad<0> signal with must be terminated with an external 10k ohm pull - down resistor. 7.1.2 8 - bit sram a synchronous bus interface 8 - b it sram bus interface doesn t use high ad<15:8> data bus, must terminate ad<15: 8 > signals with external 10 k ohm pull - down resistors . if dma transfers are not used the dack and dreq signals may be left floating or the dack signal may be terminated with external 10k ohm pull - down resistor. f t 3 1 3 h o e _ n / r e _ n / r d _ n c s _ e / c s _ n w e _ n / w r _ n a d < 1 5 : 0 > a < 7 : 0 > i n t d a c k d r e q m i c r o c o n t r o l l e r c s _ n r d _ n w r _ n a d < 1 5 : 0 > a < 7 : 0 > i n t d a c k d r e q f t 3 1 3 h o e _ n / r e _ n / r d _ n c s _ e / c s _ n w e _ n / w r _ n a d < 7 : 0 > a < 7 : 0 > i n t d a c k d r e q m i c r o c o n t r o l l e r c s _ n r d _ n w r _ n a d < 7 : 0 > a < 7 : 0 > i n t d a c k d r e q
copyright ? 201 3 future technology devices international limited 55 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 7.1.3 16 - bit nor a synchronous bus interface 16 - bit nor uses ad<15:0> signals as address and data bus. unused a<7:0> address must be terminated with external 10 k ohm pull - down resistor . if the microcontroller has no ad<0> pin for 16 - bit wide devices, the unused ad<0> signal with must be terminated with an external 10k ohm pull - down resistor. 7.1.4 8 - bit nor asynchronous bus interface 8 - bit nor uses ad<7:0> signals as address and data bus. the unused high data bus ad <15:8> and a<7:0> address bus must be terminated with external 10k ohm pull - down resistors . 7.1.5 16 - bit general multiplex asynchronous bus interface 16 - bit general multiplex uses ad<15:0> signals as address and data bus. unused a<7:0> address must be terminated with external 10k ohm pull - down resistor. f t 3 1 3 h o e _ n / r e _ n / r d _ n c s _ e / c s _ n w e _ n / w r _ n a d < 1 5 : 0 > a < 7 : 0 > i n t a d v _ n / a l e m i c r o c o n t r o l l e r c s _ n o e _ n w e _ n a d < 1 5 : 0 > i n t a d v _ n f t 3 1 3 h o e _ n / r e _ n / r d _ n c s _ e / c s _ n w e _ n / w r _ n a d < 7 : 0 > a < 7 : 0 > i n t a d v _ n / a l e m i c r o c o n t r o l l e r c s _ n o e _ n w e _ n a d < 7 : 0 > i n t a d v _ n f t 3 1 3 h o e _ n / r e _ n / r d _ n c s _ e / c s _ n w e _ n / w r _ n a d < 1 5 : 0 > a < 7 : 0 > i n t d a c k d r e q m i c r o c o n t r o l l e r c s _ n r e _ n w e _ n a d < 1 5 : 0 > i n t d a c k d r e q a d v _ n / a l e a l e
copyright ? 201 3 future technology devices international limited 56 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 if the microcontroller has no ad<0> pin for 16 - bit wide devices, the unused ad<0> signal with must be terminated with an external 10k ohm pull - down resistor. if dma transfers are not used the dack and dreq signals may be left floating or the dack signal may be terminated with external 10k ohm pull - down resistor. 7.1.6 8 - bi t general multiplex asynchronous bus interface 8 - bit general multiplex uses ad<7:0> signals as address and data bus. the unused high data bus ad<15:8> and a<7:0> address bus must be terminated with external 10k ohm pull - down resistors. if dma transfers are not used the dack and dreq signals may be left floating or the dack signal may be terminated with external 10k ohm pull - down resistor. f t 3 1 3 h o e _ n / r e _ n / r d _ n c s _ e / c s _ n w e _ n / w r _ n a d < 7 : 0 > a < 7 : 0 > i n t d a c k d r e q m i c r o c o n t r o l l e r c s _ n r e _ n w e _ n a d < 7 : 0 > i n t d a c k d r e q a d v _ n / a l e a l e
copyright ? 201 3 future technology devices international limited 57 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8 package parameters the ft313h is available in three different packages. the ft313h q is the qfn - 64 package, the ft313h l is the l qfp - 64 package and the ft313hp is the tqfp - 64 package . the solder reflow profile for all packages is described in following sections . 8.1 ft31 3h package markings 8.1.1 qfn - 64 an example of the markings on the qfn package are shown in figure 8 - 1 . the ftdi part number is too long for the 64 qfn package so in this case the last two digits are wrapped down onto the date code line. notes: 1. yyww = date code, where yy is year and ww is week number 2. marking alignment should be centre justified 3. laser marking should be used ft di xxxxxxxxxx ft313hq line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C wafer lot number 1 64 l ine 3 C ftdi part number yyww - b figure 8 - 1 qfn package markings
copyright ? 201 3 future technology devices international limited 58 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8.1.2 lqfp - 64 an example of the markings on the lqfp package are shown in figure 8 - 2 . notes: 1. yyww = date code, where yy is year and ww is week number 2. marking alignment should be centre justified 3. laser marking should be used ft di xxxxxxxxxx FT313HL line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C wafer lot number 1 64 l ine 3 C ftdi part number yyww - b figure 8 - 2 lqfp package markings
copyright ? 201 3 future technology devices international limited 59 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8.1.3 t qfp - 64 an example of the markings on the t qfp package are shown in error! reference source not found. . notes: 1. yyww = date code, where yy is year and ww is week number 2. marking alignment should be centre justified 3. laser marking should be used ft di xxxxxxxxxx ft313hp line 1 C ftdi logo l ine 4 C date code, revision l ine 2 C wafer lot number 1 64 l ine 3 C ftdi part number yyww - b figure 8 - 3 t qfp package markings
copyright ? 201 3 future technology devices international limited 60 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8.2 qfn - 64 package dimensions figure 8 - 4 qfn - 64 package markings
copyright ? 201 3 future technology devices international limited 61 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8.3 l qfp - 64 package dimensions figure 8 - 5 lqfp - 64 package markings
copyright ? 201 3 future technology devices international limited 62 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8.4 tqfp - 64 package dimensions figure 8 - 6 tqfp - 64 package markings
copyright ? 201 3 future technology devices international limited 63 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 8.5 solder reflow profile the ft313h is supplied in pb free qfn - 64 , l qf p - 64 and tqfp - 64 packages. the recommended solder reflow profile for all package options is shown in . the recommended values for the solder reflow profile are detailed in table 8 - 1 . values are shown for both a completely pb free solder process (i.e. the ft313h is used with pb free solder), and for a non - pb free solder process (i.e. the ft313h is used with non - pb free solder). profile feature pb free solder process non - pb free solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat - temperature min (t s min.) - temperature max (t s max.) - time (t s min to t s max) 150c 200c 60 to 12 0 seconds 100c 150c 60 to 120 seconds time maintained above critical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 seconds peak temperature (t p ) 260c 240c time within 5c of actual peak temperature (t p ) 20 to 40 seconds 2 0 to 4 0 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25c to peak temperature, t p 8 minutes max. 6 minutes max. table 8 - 1 reflow profile parameter values figure 8 - 7 ft313h solder reflow profile critical zone: when t is in the range t to t t e m p e r a t u r e , t ( d e g r e e s c ) time, t (seconds) 25 p t = 25 o c to t t p t p t l t preheat s t l ramp up l p ramp down t max s t min s
copyright ? 201 3 future technology devices international limited 64 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 9 ftdi chip contact information head office C glasgow, uk unit 1, 2 seaward place, centurion business park glasgow g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales 1 @ftdichip.com e - mail (support) support 1 @ftdichip.com e - mail (general enquiries) admin1@ftdichip.com branch office C taipei, taiwan 2f, no. 516, sec. 1, neihu road taipei 114 taiwan, r.o.c. tel: +886 (0) 2 8797 1330 fax: +886 (0) 2 8751 9737 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (general enquiries) tw.admin1@ftdichip.com branch office C tigard , oregon, usa 7130 sw fir loop tigard , or 97223 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) us.admin@ftdichip.com branch office C shanghai, china room 1103 , no. 666 west huai h ai road, changn ing district shanghai, 200052 china tel: +86 21 62351596 fax: +86 21 62351595 e - mail (sales) cn.sales@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com web site http://ftdichip.com system and equipment manufacturers and designers are responsible to ensure that their systems, and any future technology devices international ltd (ftdi) devices incorporated in their systems, meet all applicable safety, regulato ry and system - level performance requirements. all application - related information in this document (including application descriptions, suggested ftdi devices and other materials) is provided for reference only. while ftdi has taken care to assure it is ac curate, this information is subject to customer confirmation, and ftdi disclaims all liability for system designs and for any applications assistance provided by ftdi. use of ftdi devices in life support and/or safety applications is entirely at the users risk, and the user agrees to defend, indemnify and hold harmless ftdi from any and all damages, claims, suits or expense resulting from such use. this document is subject to change without notice. no freedom to use patents or other intellectual property r ights is implied by the publication of this document. neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written conse nt of the copyright holder. future technology devices international ltd, unit 1, 2 seaward place, centurion business park, glasgow g41 1hh, united kingdom. scotland registered company number: sc136640
copyright ? 201 3 future technology devices international limited 65 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 appendix a C references useful application notes appendix b - list of figures and tables list of figures figure 2 - 1 ft313h block diagram ................................ ................................ ................................ ... 3 figure 3 - 1 pin configuration qfn64 (top - down view) ................................ ................................ ........ 7 figure 3 - 2 pin configuration lqfp64 (top - down view) ................................ ................................ ....... 8 figure 3 - 3 pin configuration tqfp64 (top - down view) ................................ ................................ ....... 9 figure 6 - 1 read in sram mode ................................ ................................ ................................ .... 47 figure 6 - 2 write in sram mode ................................ ................................ ................................ .... 47 figure 6 - 3 read in nor mode ................................ ................................ ................................ ...... 49 figure 6 - 6 write in general multiplex mode ................................ ................................ .................... 51 figure 6 - 7 dma read and write ................................ ................................ ................................ ..... 52 figure 7 - 1 ft313h chip schematic ................................ ................................ ............................... 54 figure 8 - 1 qfn packa ge markings ................................ ................................ ................................ . 57 figure 8 - 2 lqfp package markings ................................ ................................ ................................ 58 figure 8 - 3 t qfp package markings ................................ ................................ ............................... 59 figure 8 - 4 qfn - 64 package markings ................................ ................................ ............................ 60 figure 8 - 5 lqfp - 64 package markings ................................ ................................ ........................... 61 figure 8 - 6 tqfp - 64 package markings ................................ ................................ ........................... 62 figure 8 - 7 ft313h solder reflow profile ................................ ................................ ........................ 63 list of tables table 1 - 1 ft313h numbers ................................ ................................ ................................ ............ 2 table 3 - 1 ft313h pin description ................................ ................................ ................................ .. 13 table 4 - 1 bus configuration modes ................................ ................................ ............................... 15 table 4 - 2 pin information of the bus interface ................................ ................................ ................ 15 table 4 - 3 clock frequency select ................................ ................................ ................................ .. 17 table 4 - 5 power management configuration ................................ ................................ ................... 18 table 5 - 1 overview of host controller specific registers ................................ ................................ .... 21 table 5 - 2 capability register ................................ ................................ ................................ ........ 21 table 5 - 3 structural parameter register ................................ ................................ ......................... 21 table 5 - 5 usb command register ................................ ................................ ................................ .. 24 table 5 - 6 usb status register ................................ ................................ ................................ ....... 25 table 5 - 9 periodic f rame list base address register ................................ ................................ .......... 26 table 5 - 10 current asynchronous list address register ................................ ................................ ..... 26 table 5 - 11 port status and control register ................................ ................................ .................... 29 table 5 - 12 eof time and asynchronous schedule sleep timer register ................................ ............... 30 table 5 - 14 hw mode register ................................ ................................ ................................ ....... 31 table 5 - 15 edge interrupt control register ................................ ................................ ...................... 31
copyright ? 201 3 future technology devices international limited 66 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 table 5 - 16 sw reset register ................................ ................................ ................................ ........ 32 table 5 - 17 memory address register ................................ ................................ ............................. 33 table 5 - 18 data port register ................................ ................................ ................................ ....... 33 table 5 - 19 data session length register ................................ ................................ ......................... 33 table 5 - 20 dma configuration register ................................ ................................ ........................... 35 table 5 - 21 aux memory address register ................................ ................................ ...................... 35 table 5 - 22 aux data port register ................................ ................................ ................................ . 35 table 5 - 23 sleep timer register ................................ ................................ ................................ .... 35 table 5 - 24 hc interrupt status register ................................ ................................ .......................... 37 table 5 - 25 hc interrupt status register ................................ ................................ .......................... 38 table 5 - 26 test mode register ................................ ................................ ................................ ...... 39 table 5 - 28 test parameter setting 2 register ................................ ................................ .................. 39 table 6 - 1 absolute maximum ratings ................................ ................................ ........................... 40 table 6 - 2 op erating voltage and current ................................ ................................ ....................... 41 table 6 - 3 digital i/o pin characteristics (vcc(i/o) = +3.3v, standard drive level) ............................ 41 table 6 - 4 digital i/o pin characteristics (vcc(i/o) = +2.5v, standard drive level) ............................ 42 table 6 - 5 digital i/o pin characteristics (vcc(i/o) = +1.8v, standard drive level) ............................ 42 table 6 - 6 usb i/o pin (usbdp, usbdm) characteristics ................................ ................................ .. 44 table 6 - 7 5v toleran t pin (psw_n, oc_n, vbus) characteristics ................................ ...................... 44 table 6 - 8 system clock characteristics ................................ ................................ .......................... 45 table 6 - 9 analog i/o pins characteristics ................................ ................................ ....................... 45 table 6 - 11 nor pio timing ................................ ................................ ................................ .......... 48 ta ble 6 - 12 general multiplex pio timing ................................ ................................ ........................ 50
copyright ? 201 3 future technology devices international limited 67 document no.: ft_000589 ft313h usb2.0 hs host controller datasheet version 1.2 clearance no.: ftdi# 318 appendix c - revision history document title: usb host ic ft3 13h document reference no.: ft_000589 clearance no.: ftdi# 318 product page: http://www.ftdichip.com/ftproducts.htm document feedback: ds_ft31 3h version 1.0 initial release oct 2012 version 1.1 formatting tidy up nov 2012 version 1. 2 add package markings sep 201 3

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